A low power, wide operating frequency and high noise immunity half-digital phased-locked loop

In this paper, a low power, wide operating frequency and high noise immunity half-digital phase locked loop (HDPLL) is proposed and analyzed. A novel voltage-controlled oscillator (VCO) is proposed and used to improve linear V-f characteristic and reduce the total power consumption for the HDPLL design. By HSPICE simulation results, the power dissipation of the novel VCO can be reduced over 50% in comparison to conventional VCO. Moreover, the novel VCO also has good immunity in noises and wide operating frequencies.