Efficient architecture and implementations of AES

An equivalent optimized sub-pipelined architecture is proposed to implement the AES, every round including encryption and decryption needs one clock cycle. The SubBytes/InvSubBytes operation using composite field arithmetic in GF(2⁴) and BlockRAMs respectively. In addition, an efficient key expansion which supports the output of 128 bits key per cycle and allows key changes every cycle is also presented. The novel pipelined design can achieve a throughput of 82.65Gbps on a Xilinx Virtex-4 xc4vlx100 device with composite field implementation of the SubBytes operation. By using 40 BlockRAMs and 8901 slices, the throughput of 64 Gbps is achieved with a frequency of 500MHz.These two designs´ throughput/area rate are all over 6 Mbps/Slice indicate that our designs are low-cost for high-speed implementation.