High-speed low-complexity implementation for data weighted averaging algorithm [ΣΔ modulator applications]

Author

Lee, Da-Huei ; Li, Ching-Chung ; Kuo, Tai-Haur

Author_Institution

Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan

fYear

2002

fDate

2002

Firstpage

283

Lastpage

286

Abstract

In this paper, a high-speed, low-complexity implementation of a data weighted averaging (DWA) algorithm is presented. Different from other published implementations, the maximum speed-limited function of the DWA algorithm, decoding for control signal generation and adding for register value updating, are replaced by carry look-ahead and rotating. Additionally, register simplification is adopted to reduce area costs. This design, in 0.25 μm CMOS, for a 3-bit 8-element example can operate at a 800 MHz clock rates for post-layout simulations, and costs only 254 transistors.

Keywords

CMOS logic circuits; adders; carry logic; circuit simulation; decoding; integrated circuit design; integrated circuit modelling; logic CAD; logic simulation; sigma-delta modulation; 0.25 micron; 3 bit; 800 MHz; DWA algorithm maximum speed-limited function; SDM; area cost reduction; carry look-ahead; clock rate; control signal generation decoding; data weighted averaging algorithms; high-speed low-complexity CMOS implementation; multibit sigma-delta modulators; register simplification; register value update adding; rotating operation; sigma-delta ADC; transistor number requirements; Circuits; Cities and towns; Costs; DH-HEMTs; Data engineering; Decoding; Delta-sigma modulation; Logic; Physics; Signal generators;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2002. Proceedings. 2002 IEEE Asia-Pacific Conference on

Print_ISBN

0-7803-7363-4

Type

conf

DOI

10.1109/APASIC.2002.1031587

Filename

1031587