Title :
Design of a header processor for the PSi implementation of the logical link control protocol in LANs
Author :
Morales, Fernando A. ; Abu-Amara, Hosame
Author_Institution :
Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
Abstract :
Fiber optic communications offer a combination of high bandwidth, low error probability, and gigabit transmission capacity. To take advantage of the data transmission rates offered by a fiber optic transmission medium, it is essential to have network processing components that can cope with these rates. One approach to removing the protocol processing bottleneck present in network layers is the PSi architecture. PSi consists of header, connection, and output processors. In this paper, we design a RISC architecture for the PSi header processor. The architecture consists of a two stage pipeline microprogrammed processor with a clock frequency of 50 Megahertz and a throughput of one million packets per second. The specific protocol for which this processor was microprogrammed is the Logical Link Control IEEE 802.2 protocol for LANs
Keywords :
local area networks; network interfaces; optical links; performance evaluation; protocols; reduced instruction set computing; special purpose computers; IEEE 802.2 protocol; LANs; PSi; RISC architecture; data transmission rates; fiber optic communications; gigabit transmission capacity; header processor; logical link control protocol; pipeline microprogrammed processor; protocol processing bottleneck; Bandwidth; Capacity planning; Clocks; Data communication; Error probability; Optical fiber communication; Optical fibers; Pipelines; Protocols; Reduced instruction set computing;
Conference_Titel :
High Performance Distributed Computing, 1994., Proceedings of the Third IEEE International Symposium on
Conference_Location :
San Francisco, CA
Print_ISBN :
0-8186-6395-2
DOI :
10.1109/HPDC.1994.340235
