DocumentCode :
2234634
Title :
Lower bounds on test resources for scheduled data flow graphs
Author :
Parulkar, Ishwar ; Gupta, Sandeep K. ; Breuer, Melvin A.
Author_Institution :
Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
fYear :
1996
fDate :
3-7 Jun, 1996
Firstpage :
143
Lastpage :
148
Abstract :
Lower bound estimations of resources at various stages of high-level synthesis are essential to guide synthesis algorithms towards optimal solutions. In this paper we present lower bounds on the number of test resources (i.e. test pattern generators, signature analyzers and CBILBO registers) required to test a synthesized data path using built-in self-test (BIST). The estimations are performed on scheduled data flow graphs and provide a practical way of selecting or modifying module assignments and schedules such that the resulting synthesized data path requires a small number of test resources to test itself
Keywords :
built-in self test; data flow graphs; logic testing; CBILBO registers; built-in self-test; data flow graphs; high-level synthesis; signature analyzers; test pattern generators; test resources; Automatic testing; Built-in self-test; Flow graphs; High level synthesis; Logic testing; Pattern analysis; Performance evaluation; Permission; System testing; Test pattern generators;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference Proceedings 1996, 33rd
Conference_Location :
Las Vegas, NV
ISSN :
0738-100X
Print_ISBN :
0-7803-3294-6
Type :
conf
DOI :
10.1109/DAC.1996.545561
Filename :
545561
Link To Document :
بازگشت