Title :
Evaluating the effectiveness of a software fault-tolerance technique on RISC- and CISC-based architectures
Author :
Rebaudengo, M. ; Reorda, M. Sonza ; Violante, M. ; Cheynet, P. ; Nicolescu, B. ; Velazco, R.
Author_Institution :
Dipt. di Autom. e Inf., Politecnico di Torino, Italy
Abstract :
This paper deals with a method able to provide a microprocessor-based system with safety capabilities by modifying the source code of the executed application, only. The method exploits a set of transformations which can automatically be applied, thus greatly reducing the cost of designing a safe system, and increasing the confidence in its correctness. Fault Injection experiments have been performed on a sample application using two different systems based on CISC and RISC processors. Results demonstrate that the method effectiveness is rather independent of the adopted platform
Keywords :
computer architecture; error detection; reduced instruction set computing; software fault tolerance; software performance evaluation; CISC processors; CISC-based architectures; RISC processors; RISC-based architectures; code errors; data errors; fault Injection experiments; microprocessor-based system; safety capabilities; software fault-tolerance technique; source code modification; transformations; Application software; Circuit faults; Computer applications; Costs; Design methodology; Fault tolerance; Fault tolerant systems; Hardware; Laboratories; Safety devices;
Conference_Titel :
On-Line Testing Workshop, 2000. Proceedings. 6th IEEE International
Conference_Location :
Palma de Mallorca
Print_ISBN :
0-7695-0646-1
DOI :
10.1109/OLT.2000.856606
