Design and implementation of global reduction operations across ATM networks

Author

Huang, Chengchang ; McKinley, Philip K.

Author_Institution

Dept. of Comput. Sci., Michigan State Univ., East Lansing, MI, USA

fYear

1994

fDate

2-5 Aug 1994

Firstpage

43

Lastpage

50

Abstract

The paper presents the results of an investigation into the efficient implementation of reduction operations for cluster-based parallel computing across asynchronous transfer mode (ATM) local area networks. The study combines graph theoretical analysis with experimentation on an ATM network. Different reduction algorithms are analyzed in terms of the amount of message traffic produced and the number of message-passing steps required. This analysis, which indicates how to take advantage of switch-based interconnects and hardware multicast communication, is applied to the development of both N/1 and N/K reduction protocols. Performance measurements from implementations on a three-switch ATM testbed are presented to support the analytical results

Keywords

asynchronous transfer mode; graph theory; local area networks; message passing; parallel processing; ATM local area networks; ATM networks; N/1; N/K reduction protocols; asynchronous transfer mode local area networks; cluster-based parallel computing; global reduction operations; graph theoretical analysis; hardware multicast communication; message traffic; message-passing steps; performance measurements; switch-based interconnects; three-switch ATM testbed; Algorithm design and analysis; Asynchronous transfer mode; Clustering algorithms; Communication switching; Hardware; LAN interconnection; Local area networks; Multicast algorithms; Parallel processing; Telecommunication traffic;

fLanguage

English

Publisher

ieee

Conference_Titel

High Performance Distributed Computing, 1994., Proceedings of the Third IEEE International Symposium on

Conference_Location

San Francisco, CA

Print_ISBN

0-8186-6395-2

Type

conf

DOI

10.1109/HPDC.1994.340261

Filename

340261