DocumentCode :
2235414
Title :
High level synthesis methodology for on-line testability optimization
Author :
Naal, M.A. ; Simeu, E.
Author_Institution :
TIMA Lab., Grenoble, France
fYear :
2000
fDate :
2000
Firstpage :
201
Lastpage :
206
Abstract :
Introducing testability considerations as soon as possible in the design process results in more testable design with reduced area overhead. A very important improvements can be carried out before the scheduling step. An optimization which takes effect at behavioral specifications and leads to production of an improved scheduling is proposed by this study. This optimization is good for improving not only on-line testability but also for some other objectives in the obtained synthesis
Keywords :
data flow graphs; design for testability; high level synthesis; scheduling; area overhead; behavioral specifications; high level synthesis methodology; on-line testability optimization; scheduling; Algorithm design and analysis; Automatic testing; Circuit testing; Communication system control; Hardware; High level synthesis; Magnetic heads; Optimization methods; Process design; Resource management;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
On-Line Testing Workshop, 2000. Proceedings. 6th IEEE International
Conference_Location :
Palma de Mallorca
Print_ISBN :
0-7695-0646-1
Type :
conf
DOI :
10.1109/OLT.2000.856637
Filename :
856637
Link To Document :
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