Title :
Improving fault coverage in system tests
Author :
Sosnowski, Janusz
Author_Institution :
Inst. of Comput. Sci., Warsaw Univ. of Technol., Poland
Abstract :
The paper is devoted to the problem of self-testing in system environment (field diagnosis and maintenance at the end user). It discusses test process decomposition in the context of increasing hardware complexity and proliferation of embedded DFT and BIST circuitry in the commercial off-the shelf VLSI chips (COTS). Test observability is improved with the use of various on-line monitoring mechanisms. To optimize test effectiveness we use special tools based on direct and indirect fault coverage analysis
Keywords :
VLSI; built-in self test; design for testability; fault diagnosis; integrated circuit testing; observability; BIST; COTS; DFT; direct fault coverage analysis; field diagnosis; hardware complexity; indirect fault coverage analysis; off-the shelf VLSI chips; on-line monitoring mechanisms; self-testing; system tests; test effectiveness; test observability; test process decomposition; System testing;
Conference_Titel :
On-Line Testing Workshop, 2000. Proceedings. 6th IEEE International
Conference_Location :
Palma de Mallorca
Print_ISBN :
0-7695-0646-1
DOI :
10.1109/OLT.2000.856638
