Title :
A performance-enhanced parallel scheduling algorithm for MIQ switches providing a QoS guarantee
Author :
Kim, Hakyong ; Yoon, Hyunho ; Kim, Kiseon ; Lee, Yongtak
Author_Institution :
Dept. Inf. & Commun, Kwang-Ju Inst. of Sci. & Technol., Kwangju, South Korea
Abstract :
A novel parallel scheduling algorithm, namely a parallel solitary-request-first (PSRF) algorithm, is proposed to improve the performance of the multiple input-queued (MIQ) switch. The proposed algorithm is basically based on the three-phase scheme consisting of request, grant, and accept phases. The essential idea of PSRF is to select the solitary requests with preference. By doing so, PSRF enhances the throughput of the MIQ switch whose input has less number of queues than the switch size. Simulation results for the i.i.d. Bernoulli traffic demonstrate that 2 or 4 queues are appropriate in terms of simplicity, efficiency, and operation speed. Further, to provide a QoS guarantee in the MIQ switch, we developed an enhanced PSRF scheduler which is a kind of the hierarchical or hybrid scheduling algorithm. Hierarchical scheduling is a mixture of a static scheduling with a dynamic scheduling. That is, after finding out an optimal set of input-output matchings, the scheduler chooses one VC connection or a cell in the corresponding virtual queue so as to provide a high throughput as well as the QoS guarantee
Keywords :
digital simulation; optimisation; packet switching; parallel algorithms; quality of service; queueing theory; telecommunication traffic; MIQ switches; QoS guarantee; VC connection; accept phase; dynamic scheduling; efficiency; grant phase; hierarchical scheduling algorithm; hybrid scheduling algorithm; i.i.d. Bernoulli traffic; input-output matching; multiple input-queued switch; operation speed; packet switch; parallel solitary-request-first algorithm; performance-enhanced parallel scheduling algorithm; request phase; simulation results; static scheduling; switch size; throughput; virtual queue; Communication switching; Dynamic scheduling; Electronic mail; Hardware; Impedance matching; Scheduling algorithm; Switches; Throughput; Traffic control; Uniform resource locators;
Conference_Titel :
High Performance Switching and Routing, 2000. ATM 2000. Proceedings of the IEEE Conference on
Conference_Location :
Heidelberg
Print_ISBN :
0-7803-5884-8
DOI :
10.1109/HPSR.2000.856645