Title :
Microarchitecture Sensitive Empirical Models for Compiler Optimizations
Author :
Vaswani, Kapil ; Thazhuthaveetil, Matthew J. ; Srikant, Y.N. ; Joseph, P.J.
Author_Institution :
Indian Inst. of Sci., Bangalore
Abstract :
This paper proposes the use of empirical modeling techniques for building microarchitecture sensitive models for compiler optimizations. The models we build relate program performance to settings of compiler optimization flags, associated heuristics and key microarchitectural parameters. Unlike traditional analytical modeling methods, this relationship is learned entirely from data obtained by measuring performance at a small number of carefully selected compiler/microarchitecture configurations. We evaluate three different learning techniques in this context viz. linear regression, adaptive regression splines and radial basis function networks. We use the generated models to a) predict program performance at arbitrary compiler/microarchitecture configurations, b) quantify the significance of complex interactions between optimizations and the microarchitecture, and c) efficiently search for ´optimal´ settings of optimization flags and heuristics for any given micro architectural configuration. Our evaluation using benchmarks from the SPEC CPU2000 suites suggests that accurate models (< 5% average error in prediction) can be generated using a reasonable number of simulations. We also find that using compiler settings prescribed by a model-based search can improve program performance by as much as 19% (with an average of 9.5%) over highly optimized binaries
Keywords :
optimising compilers; radial basis function networks; SPEC CPU2000; adaptive regression splines; arbitrary compiler configurations; compiler optimizations; empirical modeling; linear regression; microarchitecture configurations; microarchitecture sensitive empirical models; microarchitecture sensitive models; optimal settings; optimization flags; radial basis function networks; Analytical models; Buildings; Design optimization; Hardware; Microarchitecture; Optimizing compilers; Performance analysis; Predictive models; Prefetching; Program processors;
Conference_Titel :
Code Generation and Optimization, 2007. CGO '07. International Symposium on
Conference_Location :
San Jose, CA
Print_ISBN :
0-7695-2764-7
DOI :
10.1109/CGO.2007.25