DocumentCode
2235765
Title
Cycle time reduction program at ACL
Author
Boebel, F.G. ; Ruelle, O.
Author_Institution
Siemens SA, Corbeil-Essonnes, France
fYear
1996
fDate
12-14 Nov 1996
Firstpage
165
Lastpage
168
Abstract
In this paper we focus on the results of the DRAM production cycle time team with special emphasis on: how does CT translate into productivity; what tools are needed for effective CT analysis including daily going rate (DGR) issues; how to find and how to fight the main CT detractors The results are compared with the real world execution at the SIEMENS/IBM Advanced CMOS line (ACL) in Essonnes-Corbeil
Keywords
CMOS memory circuits; DRAM chips; human resource management; integrated circuit manufacture; production control; ACL; CT analysis; DRAM production; Siemens/IBM advanced CMOS line; cycle time reduction; daily going rate; productivity; Costs; Data mining; Job shop scheduling; Logistics; Manufacturing; Mass production; Productivity; Random access memory; Semiconductor device manufacture; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Advanced Semiconductor Manufacturing Conference and Workshop, 1996. ASMC 96 Proceedings. IEEE/SEMI 1996
Conference_Location
Cambridge, MA
ISSN
1078-8743
Print_ISBN
0-7803-3371-3
Type
conf
DOI
10.1109/ASMC.1996.557990
Filename
557990
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