Performance of time stepping mechanism for parallel cell rate simulation of ATM networks

A time stepping approach has been adopted by RACE project R2059 ICM for time synchronisation in an event driven ATM network simulator. This paper describes the results of a study into the effects of varying the size of the timestep, on both the measured traffic characteristics and the simulation speed. A simplified version of the ICM cell rate simulator is used; the traffic events are described as cell rate changes but switches do not perform burst scale queueing. Any excess cell rate is immediately lost. When the size of the timestep is greater than the link delay, the propagation of cell rate change events is synchronised with the timestep boundaries. A simulator is proposed in which the size of the timestep can be varied dynamically from one level to another, in order to optimise the performance. Preliminary results indicate that this large timestep value should be no greater than one tenth of the average burst length of the source traffic