Modeling and Formal Control of Partial Dynamic Reconfiguration

Author

Guillet, Sébastien ; De Lamotte, Florent ; Rutten, Éric ; Gogniat, Guy ; Diguet, Jean-Philippe

Author_Institution

Lab.-STICC, Univ. de Bretagne Sud, Lorient, France

fYear

2010

fDate

13-15 Dec. 2010

Firstpage

31

Lastpage

36

Abstract

This paper introduces an approach for the safe design and modeling of dynamically reconfigurable FPGA based Systems-on-Chip. This approach is carried out in a design framework, GASPARD2, dedicated to high-performance embedded systems modeling using the OMG standard profile UML/MARTE. Information employed by the reconfiguration mechanism is identified to be extracted from MARTE models in order to synthesize a controller using a formal technique which significantly simplifies the correct design of reconfiguration control. This methodology is then demonstrated in a case study.

Keywords

Unified Modeling Language; control system synthesis; embedded systems; field programmable gate arrays; logic design; reconfigurable architectures; system-on-chip; Gaspard2 design framework; OMG standard profile; UML-MARTE; controller synthesis; dynamically reconfigurable FPGA based system-on-chip; high-performance embedded system modeling; partial dynamic reconfiguration; reconfiguration control design; Discrete Controller Synthesis; MARTE; UML;

fLanguage

English

Publisher

ieee

Conference_Titel

Reconfigurable Computing and FPGAs (ReConFig), 2010 International Conference on

Conference_Location

Quintana Roo

Print_ISBN

978-1-4244-9523-8

Electronic_ISBN

978-0-7695-4314-7

Type

conf

DOI

10.1109/ReConFig.2010.56

Filename

5695277