Proceedings EURO-DAC ´96. European Design Automation Conference with EURO-VHDL ´96 and Exhibition

The following topics were dealt with: analogue and mixed-mode simulation; low-power synthesis; design experience; timing modelling; design flow and design management; partitioning; logic and finite state machine synthesis; binary decision diagram optimization techniques; codesign methodology and cospecification; system-level design and synthesis; new aspects on testing; cosimulation; formal verification techniques in industry (equivalence checking vs. property checking); key technologies and CAD of microsystems; asynchronous synthesis and storage optimization; modelling and simulation of microsystems and multi-layer routing in PCBs; timing issues in synthesis; physical design for deep submicron LSI; architectural synthesis techniques; electronic design automation tools and the submicron wall; CAD for analogue circuits; analysis tools; beyond VHDL; object-oriented extensions to VHDL; fault modelling and design for testability; formal methods; modelling methodologies; synthesis with VHDL; system-level design; VHDL and mixed signal design; and the Open Forum Model