DocumentCode
2236297
Title
Vector-logical diagnosis method for SOC functionalities
Author
Hahanov, Vladimir ; Guz, Olesya ; Kulbakova, Natalya ; Davydov, M.
Author_Institution
Comput. Eng. Fac., Kharkov Nat. Univ. of Radioelectron., Kharkov, Ukraine
fYear
2008
fDate
9-12 Oct. 2008
Firstpage
159
Lastpage
162
Abstract
Models and methods of vector-logical diagnosis of SoC functionalities in real time are proposed. Algebra-logical procedures of embedded fault diagnosis by means of DNF synthesis that forms all functionality diagnosis solutions are described. The method is based on use the fault detection table that is result of fault simulation.
Keywords
algebra; fault simulation; system-on-chip; DNF synthesis; SOC functionalities; algebra-logical procedures; embedded fault diagnosis; fault detection table; fault simulation; functionality diagnosis solutions; vector-logical diagnosis; Electrical fault detection; Fault detection; Fault diagnosis; Integrated circuit modeling; System-on-a-chip; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design & Test Symposium (EWDTS), 2008 East-West
Conference_Location
Lviv
Print_ISBN
978-1-4244-3402-2
Electronic_ISBN
978-1-4244-3403-9
Type
conf
DOI
10.1109/EWDTS.2008.5580136
Filename
5580136
Link To Document