Cascading Deep Pipelines to Achieve High Throughput in Numerical Reduction Operations

This work proposes a cascaded and pipelined (CAP) reconfigurable architecture to achieve high throughput in executing numerical reduction operations commonly found in many scientific computations by (1) cascading multiple deeply-pipelined floating-point arithmetic cores to match the inherent computing structure underlying target operations, (2) interleaving multiple computing threads to eliminate the data hazards caused by the feedback connection around long pipelines, and (3) judiciously balancing the granularity of grouping pipelines with overall achievable throughput. A CAP machine with 28 processing nodes was implemented with a Virtex-5 FPGA (XCV5LX155T-2) on a BEE3 (Berkeley Emulation Engine) platform. For a wide variety of convex optimization problems found in the decoding stage of compressive sensing, when comparing running the L1-MAGIC software package on a 2.4 GHz Core 2 Duo Intel processor, the CAP demonstrates a 50× speedup on average, with a peak throughput of 6.34 GFLOPS (Giga Floating-Point Operations per Second).