DocumentCode
2236465
Title
Reliable NoC architecture utilizing a robust rerouting algorithm
Author
Alaghi, Armin ; Sedghi, Maryam ; Karimi, N. ; Fathy, Mahmood ; Navabi, Zainalabedin
Author_Institution
Electr. & Comput. Eng. Dept., Univ. of Tehran, Tehran, Iran
fYear
2008
fDate
9-12 Oct. 2008
Firstpage
200
Lastpage
203
Abstract
Moving towards reconfigurability is an approach to increase fault tolerance on System-on-Chip design. In this paper, we propose a self-reconfigurable NoC architecture utilizing a robust rerouting method. At first, an offline test strategy for locating system-level faults in NoC switch ports is utilized. Using the information achieved in the test phase, every switch reconfigures itself to avoid routing packets through faulty links by utilizing our local rerouting method. The proposed rerouting method is evaluated using a Transaction-Level platform. Experimental results show that our proposed rerouting method delivers all the packets in a faulty NoC successfully and has a less communication overhead compared to a pure flooding method.
Keywords
fault location; fault tolerance; integrated circuit design; integrated circuit reliability; integrated circuit testing; network-on-chip; reconfigurable architectures; switches; NoC switch ports; fault tolerance; offline test strategy; robust rerouting algorithm; self-reconfigurable NoC architecture; system-level fault location; system-on-chip design; transaction-level platform; Circuit faults; Computer architecture; Fault tolerance; Fault tolerant systems; Routing; Switches; System-on-a-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
Design & Test Symposium (EWDTS), 2008 East-West
Conference_Location
Lviv
Print_ISBN
978-1-4244-3402-2
Electronic_ISBN
978-1-4244-3403-9
Type
conf
DOI
10.1109/EWDTS.2008.5580142
Filename
5580142
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