Utilizing HDL simulation engines for accelerating design and test processes

This paper introduces a complete test package in VHDL that makes it possible to simulate faults and generate test patterns for a component during its design process. Different approaches on test applications can be combined and then be applied to combinational, sequential and scan-based circuits in a fully configurable and convenient environment. To reveal the capabilities of VHDL in test configurations, we used two different approaches for fault simulation and evaluated them with random tests.