DocumentCode
2236507
Title
Diagnosis of SoC faulty memory cells for embedded repair
Author
Hahanov, Vladimir ; Litvinova, Eugenia ; Krasnoyaruzhskaya, Karina ; Galagan, Sergey
Author_Institution
Comput. Eng. Fac., Kharkov Nat. Univ. of Radioelectron., Kharkov, Ukraine
fYear
2008
fDate
9-12 Oct. 2008
Firstpage
143
Lastpage
148
Abstract
A method of optimal memory fault repair that differs from analogs by application of algebra-logical technology of fault covering by two-dimensional memory matrix topology is proposed. It results in obtaining minimal and full solutions for subsequent repair in real time, which is based on utilization of spares in memory rows and columns.
Keywords
algebra; digital storage; fault diagnosis; network topology; system-on-chip; SoC faulty memory cells; algebra-logical technology; embedded repair; fault covering; fault diagnosis; memory columns; memory fault repair; memory rows; two-dimensional memory matrix topology; Boolean functions; Construction industry; Maintenance engineering; Measurement; Minimization; Real time systems; System-on-a-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
Design & Test Symposium (EWDTS), 2008 East-West
Conference_Location
Lviv
Print_ISBN
978-1-4244-3402-2
Electronic_ISBN
978-1-4244-3403-9
Type
conf
DOI
10.1109/EWDTS.2008.5580144
Filename
5580144
Link To Document