Improving the Reliability of a FPGA Using Fault-Tolerance Mechanism Based on Magnetic Memory (MRAM)

The current SRAM based FPGA, are more and more susceptible to Single Event Upset (SEU) due to Neutron particle interference. The problem is exasperated reducing the CMOS submicronic scale in the manufacturing process, specially for the next generation of SRAM-based FPGAs. Nowadays is common practice for SRAM manufactories to embed fault tolerant mechanisms like Error-Correcting Code schemes in SRAM memory banks for CMOS technology below 90 nm, to mitigate SEU. The present work proposes an approach to improve the reliability of the FPGAs, regarding SEU events at ground level for the future submicronic scale technologies proposing the adoption of Magnetic Random Access Memories (MRAMs) cells into a simple fault-tolerant system for FPGAs manufactured below 65 nm submicronic scale.