Partitioning, floor planning, detailed placement and routing techniques for schematic generation of analog netlist

The schematic generator has become a very powerful debug tool in EDA in all of the flows whether it is RTL, Synthesis, formal verification or at the layout level. The paper talks about various challenges in showing a "good" schematic for a spice netlist and then proposes novel algorithms used to generate the schematic. The paper also links various schematic generation stages with techniques used by P&R tools such as floor planning, global routing, and detailed placement and routing. The transistor level schematic generation differs from the gate level schematic, in that a set of transistors in spice netlist forms a logic and these set of transistors need to be placed together in some symmetry to represent the logic. The paper addresses the challenges that lie in placing and extracting these components which represent logic or a current flow or cascade effect.