DocumentCode
2236953
Title
Modeling and Simulation of Reconfigurable Processors in Grid Networks
Author
Nadeem, M. Faisal ; Ahmadi, Mahmood ; Nadeem, M. ; Wong, Stephan
Author_Institution
Comput. Eng. Lab., Delft Univ. of Technol., Delft, Netherlands
fYear
2010
fDate
13-15 Dec. 2010
Firstpage
226
Lastpage
231
Abstract
Traditional grid networks employ general purpose processors (GPPs) as their main processing elements. Incorporating reconfigurable processing elements in such networks can be a promising technology to increase their performance and flexibility. Many grid networks, such as Tera Grid, are already utilizing reconfigurable hardware resource as a processing element. In this paper, we propose queuing models for grid networks that incorporate the following processing elements: a GPP, a reconfigurable element (RE), and a hybrid element (combining a GPP with an RE). The proposed models are validated by taking average response time of these models as validation metric. The comparison of experimental (simulation) and analytical results suggest that the total average error is less than 3.5%.
Keywords
grid computing; queueing theory; reconfigurable architectures; general purpose processor; grid network; hybrid element; queuing model; reconfigurable element; reconfigurable hardware resource; reconfigurable processor; Jackson network; Reconfigurable computing; grid networks; queuing model;
fLanguage
English
Publisher
ieee
Conference_Titel
Reconfigurable Computing and FPGAs (ReConFig), 2010 International Conference on
Conference_Location
Quintana Roo
Print_ISBN
978-1-4244-9523-8
Electronic_ISBN
978-0-7695-4314-7
Type
conf
DOI
10.1109/ReConFig.2010.50
Filename
5695310
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