Logic/resistive-switching hybrid transistor for two-bit-per-cell storage

Author

Wu, Shih-Chieh ; Lo, Chieh ; Hou, Tuo-Hung

Author_Institution

Dept. of Electron. Eng., Nat. Chiao-Tung Univ., Hsinchu, Taiwan

fYear

2012

fDate

23-25 April 2012

Firstpage

1

Lastpage

2

Abstract

Various bias schemes in the RS-TFT have been comprehensively investigated. As shown in Table I, the V_D-biased bipolar RS is superior for the logic/RS hybrid operation with the ability of two-bit-per-cell storage because of its large program margin, localized filament location, negligible V_TH shift, and suppressed gate leakage current. In comparison with other embedded memory technologies, the proposed RS-TFT in this work not only is compatible with logic CMOS technology, but also provides comparable memory performance with a very competitive cell size.

Keywords

CMOS logic circuits; CMOS memory circuits; embedded systems; leakage currents; random-access storage; thin film transistors; RS-TFT; bipolar RS; comparable memory performance; embedded memory technologies; gate leakage current; localized filament location; logic CMOS technology; logic resistive-switching hybrid transistor; program margin; two-bit-per-cell storage; Hafnium compounds; Leakage current; Logic gates; Nickel; Silicon; Thin film transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems, and Applications (VLSI-TSA), 2012 International Symposium on

Conference_Location

Hsinchu

ISSN

1930-8868

Print_ISBN

978-1-4577-2083-3

Type

conf

DOI

10.1109/VLSI-TSA.2012.6210103

Filename

6210103