DocumentCode
2237239
Title
P-channel Schottky barrier nanowire SONOS memory with low-voltage operations and excellent reliability
Author
Chang, Wei ; Shih, Chun-Hsing ; Wu, Wen-Fa ; Lien, Chenhsin
Author_Institution
Inst. of Electron. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
fYear
2012
fDate
23-25 April 2012
Firstpage
1
Lastpage
2
Abstract
An ultralow voltage p-channel Schottky barrier nanowire SONOS memory is reported experimentally with excellent reliability. By applying pure metallic Schottky barrier S/D, the nanowire SONOS memory can operate at a gate voltage of -7V to -11V for hole programming, and 5V to 7V for electron erasing. This Schottky barrier cell exhibits superior 10K cycling and 125°C retention for practical applications.
Keywords
Schottky barriers; field effect memory circuits; integrated circuit reliability; low-power electronics; nanowires; P-channel Schottky barrier nanowire; SONOS memory; Schottky barrier cell; electron erasing; hole programming; low-voltage operations; reliability; ultralow voltage Schottky barrier nanowire; voltage -7 V to -11 V; voltage 5 V to 7 V; Computer architecture; Logic gates; Programming; SONOS devices; Schottky barriers; Silicon; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, Systems, and Applications (VLSI-TSA), 2012 International Symposium on
Conference_Location
Hsinchu
ISSN
1930-8868
Print_ISBN
978-1-4577-2083-3
Type
conf
DOI
10.1109/VLSI-TSA.2012.6210104
Filename
6210104
Link To Document