MOSFETs transitions towards fully depleted architectures

Summary form only given. Recent device developments and achievements have demonstrated that undoped channel Fully depleted SOI devices are becoming a serious alternative to Bulk technologies for 20nm node and below. These architectures have proven that they can provide high drive current together with ensuring low static and dynamic power. This paper gives an overview of the main advantages provided by Fully Depleted technologies, as well as the key challenges that need to be addressed. Electrostatic integrity, drivability, variability and scalability are addressed through silicon data and TCAD analyses. Unique features of planar architectures such as solutions to the Multiple VT challenges and non logic devices (ESD, I/Os) are also reported.