Hardware performance estimation by dynamic scheduling

Hardware/software partition is an essential step in current complex digital design. During the last decades, several partition methodologies have been proposed, most of them based on software and hardware performance estimations. A common limitation of these methodologies is that the source code of the hardware part has to be modified and/or adapted in order to obtain accurate hardware estimations. This paper presents a new hardware performance estimation tool that works with high-level system specifications. An important advantage of the proposal is that the same source code can be used for hardware and software estimations. In order to obtain the execution time of the hardware partition during system simulation, every element of the algorithm is decomposed into primitive operations that are dynamically queued in a sliding-window of limited size. Several hardware-related restrictions are applied to this queue and two dynamic scheduling methodologies are used. The first scheduling methodology enables the estimation of a low bound of the hardware execution time. This estimation should be faster than any implementation of the hardware part. The second methodology provides an upper limit of the execution time that represents a hardware implementation with a low synthesis effort. These limits help designers to decide if it worthwhile to adapt part of the code to be implemented in hardware.