Title :
Buffer performance study of the VC merging capable ATM-based MPLS switch by simulation
Author :
Xu, Shao ; Wei, Ding
Author_Institution :
Training Center, Beijing Univ. of Posts & Telecommun., China
Abstract :
In order to improve the scalability of an ATM-based MPLS network, ATM switches should support VC merging. An effective method is to add an extra reassemble buffer in the ATM switches´ output ports. On the basis of precise analysis of the VC merging physical procedure, a logic architecture of simulation is proposed. The average waiting time and average queue length in different conditions are studied via simulation and some valuable conclusions obtained. This simulation measure in the paper also has reference value for the design of VC merging-capable ATM-based MPLS switches
Keywords :
asynchronous transfer mode; buffer storage; protocols; queueing theory; telecommunication network management; ATM; MPLS switch; VC merging; buffer management; buffer performance; logic architecture; multi-protocol label switching; queue length; reassemble buffer; scalability; simulation; virtual circuit; waiting time; Asynchronous transfer mode; Logic; Merging; Multiprotocol label switching; Packet switching; Switches; Telecommunication switching; Telecommunication traffic; Traffic control; Virtual colonoscopy;
Conference_Titel :
Info-tech and Info-net, 2001. Proceedings. ICII 2001 - Beijing. 2001 International Conferences on
Conference_Location :
Beijing
Print_ISBN :
0-7803-7010-4
DOI :
10.1109/ICII.2001.983563
