Title :
Optimization of control gate material and structure for enhancing 20nm 64Gb NAND flash reliability
Author :
Kim, Hae Soo ; Lee, Kang Jae ; Han, Kwang Hee ; Seok Won Cho ; Choi, Se Kyoung ; Seo, Shin Won ; Chung, Jae Hyun ; Lee, Keun Woo ; Chung, Sung Jae ; Noh, Keum Hwan ; Youn, Tae Un ; Lee, Ju Yeab ; Lee, Min Kyu ; Han, Byeong Il ; Yi, Su Min ; Lee, Ho Seok ;
Author_Institution :
Flash Dev. Div., Hynix Semicond. Inc., Cheongju, South Korea
Abstract :
We developed the new control gate (CG) material and structure in order to overcome scaling limitation beyond 20nm NAND flash cell. New CG material can achieve excellent gap-fill without void and improvement of the Gate CD Gap (GCG). And also, by using new CG material, CG depletion between floating gate (FG) can be improved. As a result, gate coupling ratio, bit-line (BL) interference and tail-cell Vt distribution are drastically improved. These technologies play an important role in the characteristic of scaled NAND flash memory cell and reliability.
Keywords :
NAND circuits; flash memories; logic gates; NAND flash memory cell; NAND flash reliability; bit-line interference; control gate material optimization; floating gate; gate coupling ratio; scaling limitation; Couplings; Flash memory; Interference; Logic gates; Materials; Nonvolatile memory; Reliability;
Conference_Titel :
VLSI Technology, Systems, and Applications (VLSI-TSA), 2012 International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
978-1-4577-2083-3
DOI :
10.1109/VLSI-TSA.2012.6210120
