Title :
Impact of thermal budget on dopant-segregated (DS) metal S/D gate-all-around (GAA) PFETs
Author :
Akarvardar, K. ; Rodgers, M. ; Kaushik, V. ; Johnson, C.S. ; Ok, I. ; Ang, K.-W. ; Stamper, H. ; Bennett, S. ; Franca, D. ; Rao, M. ; Gausepohl, S. ; Hobbs, C. ; Kirsch, P. ; Jammy, R.
Author_Institution :
GlobalFoundries, Sunnyvale, CA, USA
Abstract :
Low temperature (T ≤ 480C after gate stack) DS Metal S/D GAA PFETs were fabricated and benchmarked to devices with S/D activation anneal (SDAA). It is shown that when DS implantation precedes gate spacer formation, devices without SDAA have higher peak Gm and IDsat, however also higher Ioff than their counterparts with SDAA. Fabricated low-thermal-budget GAA PFETs with TiN/HfO2 gate and NiPtSi S/D achieve IDsat = 0.8 mA/um and Ion/Ioff >; 2000 for VGS = -1.5 V, VDS = -1 V, and 100 nm nanowire length.
Keywords :
annealing; field effect transistors; nanowires; semiconductor doping; DS implantation; NiPtSi; S/D activation anneal; TiN-HfO2; dopant-segregated metal S/D gate-all-around PFET; gate spacer formation; low temperature DS metal S/D GAA PFET; nanowire; size 100 nm; thermal budget; voltage -1 V; voltage -1.5 V; Annealing; Implants; Logic gates; MOSFETs; Metals; Silicides; Silicon;
Conference_Titel :
VLSI Technology, Systems, and Applications (VLSI-TSA), 2012 International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
978-1-4577-2083-3
DOI :
10.1109/VLSI-TSA.2012.6210131
