DocumentCode
2238145
Title
Sensitivity analysis of iterative design processes
Author
Johnson, E.W. ; Brockman, J.B. ; Vigeland, R.
Author_Institution
Dept. of Comput. Sci. & Eng., Notre Dame Univ., IN, USA
fYear
1996
fDate
10-14 Nov. 1996
Firstpage
142
Lastpage
145
Abstract
As design processes continue to increase in complexity, it is important to base process improvements on quantitative analysis. In this paper we develop an analytical approach to analyze sequential design processes using sensitivity analysis. Two applications illustrate this approach, one involving a Pareto analysis of an ASIC design process and the other an optimization of a software design process to determine the lower bound of the process completion time.
Keywords
application specific integrated circuits; logic CAD; probability; sensitivity analysis; sequential circuits; ASIC design process; Pareto analysis; iterative design processes; optimization; process completion time; quantitative analysis; sensitivity analysis; sequential design processes; software design process; Application software; Application specific integrated circuits; Computer graphics; Computer science; Design engineering; Equations; Monitoring; Pareto analysis; Process design; Sensitivity analysis;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer-Aided Design, 1996. ICCAD-96. Digest of Technical Papers., 1996 IEEE/ACM International Conference on
Conference_Location
San Jose, CA, USA
Print_ISBN
0-8186-7597-7
Type
conf
DOI
10.1109/ICCAD.1996.569536
Filename
569536
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