DocumentCode :
2238258
Title :
Clock-driven performance optimization in interactive behavioral synthesis
Author :
Hsiao-Ping Juan ; Gajski, D.D. ; Chaiyakul, V.
Author_Institution :
Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
fYear :
1996
fDate :
10-14 Nov. 1996
Firstpage :
154
Lastpage :
157
Abstract :
In interactive behavioral synthesis, the designer can control the design process at every stage, including modifying the schedule of the design to improve its performance. In this paper, we present a methodology for performance optimization in interactive behavioral synthesis. Also proposed are several quality metrics and hints that can assist the user in utilizing the proposed methodology. When the user is optimizing the performance of the design, one important decision is the selection of a clock period. To facilitate clock selection by the user, we have developed an algorithm to estimate the effect of different clock periods on the execution time of the design. We have tested our methodology on several benchmarks. The experimental results support the proposed methodology by demonstrating an average improvement of 46.2% in design performance.
Keywords :
logic CAD; optimisation; clock selection; interactive behavioral synthesis; performance optimization; quality metrics; Algorithm design and analysis; Automatic control; Clocks; Computer science; Control system synthesis; Delay; Design optimization; Process design; Processor scheduling; Testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer-Aided Design, 1996. ICCAD-96. Digest of Technical Papers., 1996 IEEE/ACM International Conference on
Conference_Location :
San Jose, CA, USA
Print_ISBN :
0-8186-7597-7
Type :
conf
DOI :
10.1109/ICCAD.1996.569538
Filename :
569538
Link To Document :
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