PMOSFET layout dependency with embedded SiGe Source/Drain at POLY and STI edge in 32/28nm CMOS technology

Author

Song, L. ; Liang, Y. ; Onoda, H. ; Lai, C.W. ; Wallner, T.A. ; Pofelski, A. ; Gruensfelder, C. ; Josse, E. ; Okawa, T. ; Brown, J. ; Williams, R.Q. ; Holt, J. ; Weijtmans, J.W. ; Greene, B. ; Utomo, H.K. ; Lee, S.C. ; Nair, D. ; Zhang, Q. ; Zhu, C. ; Wu,

Author_Institution

Semicond. R&D Center, IBM, Hopewell Junction, NY, USA

fYear

2012

fDate

23-25 April 2012

Firstpage

1

Lastpage

2

Abstract

The eSiGe layout effect induced by PC-bounded or STI-bounded eSiGe shows impact on device performance and variability increase. For PC-bounded device, performance degradation could be explained by the mobility loss due to reducing eSiGe volume and less stress strength. For STI-bounded device, performance degradation varies, due to strong interaction between eSiGe fill morphology and device overlap capacitance. This observation was confirmed by an eSiGe fill level study. Compared to PC-bounded eSiGe, STI-bounded devices have increase variation due to eSiGe process.

Keywords

CMOS integrated circuits; Ge-Si alloys; MOSFET; CMOS technology; PMOSFET layout; POLY edge; STI edge; SiGe; SiGe source/drain; device performance; device variability; performance degradation; Degradation; Layout; Logic gates; Morphology; Performance evaluation; Stress; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems, and Applications (VLSI-TSA), 2012 International Symposium on

Conference_Location

Hsinchu

ISSN

1930-8868

Print_ISBN

978-1-4577-2083-3

Type

conf

DOI

10.1109/VLSI-TSA.2012.6210152

Filename

6210152