Title :
Gate-first TiAlN P-gate electrode for cost effective high-k metal gate implementation
Author :
Ni, C. -N ; Fu, X. ; Yoshida, N. ; Chan, O. ; Jin, M. ; Chen, H. ; Hung, S. ; Jakkaraju, R. ; Kesapragada, S. ; Lazik, C. ; Hung, R. ; Gandikota, S. ; Chang, C. -P ; Brand, A.
Author_Institution :
Appl. Mater., Santa Clara, CA, USA
Abstract :
Gate-first (GF) high-k metal gate (HKMG) for LSTP/LOP logic and DRAM periphery applications requires an efficient and low-cost effective work function (eWF) solution. We demonstrated TiAlN for pFET eWF tuning without appreciable EOT, Jg, and interface degradation. Hence TiAlN is shown to be a key enabler to realize process-friendly and cost-effective GF HKMG implementation.
Keywords :
DRAM chips; electrodes; DRAM periphery application; cost effective high-k metal gate implementation; effective work function solution; gate-first electrode; gate-first high-k metal gate; interface degradation; Annealing; Gate leakage; Logic gates; Random access memory; Tin;
Conference_Titel :
VLSI Technology, Systems, and Applications (VLSI-TSA), 2012 International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
978-1-4577-2083-3
DOI :
10.1109/VLSI-TSA.2012.6210155
