Substrate current protection in smart power IC´s

Author

Gonnard, O. ; Charitat, G. ; Lance, Ph ; Stefanov, E. ; Suquet, M. ; Bafleur, M. ; Mauran, N. ; Peyre-Lavigne, A.

Author_Institution

Lab. d´´Autom. et d´´Anal. des Syst., CNRS, Toulouse, France

fYear

2000

fDate

2000

Firstpage

169

Lastpage

172

Abstract

In this paper, we describe and characterize a parasitic current, called substrate current injection in a SMART POWER technology. This parasitic current occurs when a normally reversed bias diode becomes forward biased and can disrupt the normal IC´s functionality. We propose two design solutions able to decrease this parasitic current influence. These solutions, based on 2D simulation and on real-size measurements, are fully compatible with a standard technological process. The first one, consists in a correct guard ring polarization, in this case we can divide by 3 the injected current. The second one, based upon a special alignment for the N buried layer can decrease the parasitic current by a factor of 10

Keywords

buried layers; charge injection; integrated circuit design; integrated circuit measurement; integrated circuit modelling; overcurrent protection; power integrated circuits; 2D simulation; N buried layer; SMART POWER technology; design; forward bias; guard ring polarization; injected current; normally reversed bias diode; parasitic current; real-size measurements; smart power IC; substrate current injection; substrate current protection; CMOS analog integrated circuits; Integrated circuit technology; Isolation technology; Low voltage; Power integrated circuits; Protection; Semiconductor diodes; Size measurement; Substrates; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Semiconductor Devices and ICs, 2000. Proceedings. The 12th International Symposium on

Conference_Location

Toulouse

ISSN

1063-6854

Print_ISBN

0-7803-6269-1

Type

conf

DOI

10.1109/ISPSD.2000.856798

Filename

856798