Challenges of III–V materials in advanced CMOS logic

Author

Kirsch, P.D. ; Hill, R.J.W. ; Huang, J. ; Loh, W.Y. ; Kim, T.-W. ; Wong, M.H. ; Min, B.G. ; Huffman, C. ; Veksler, D. ; Young, C.D. ; Ang, K.W. ; Ali, I. ; Lee, R.T.P. ; Ngai, T. ; Wang, A. ; Wang, W.-E. ; Cunningham, T.H. ; Chen, Y.T. ; Hung, P.Y. ; Bers

Author_Institution

SEMATECH, Albany, NY, USA

fYear

2012

fDate

23-25 April 2012

Firstpage

1

Lastpage

2

Abstract

The superior transport properties of III-V materials are promising candidates to achieve improved performance at low power. This paper examines the module challenges of III-V materials in advanced CMOS at or beyond the 10 nm technology node, and reports VLSI compatible epi, junction, contact and gate stack process modules with Xj<;60;10nm, N_D=5×10¹⁹ cm^-3, ρ_c= 6Ω.μm² and Dit = 4×10¹² eV^-1 cm^-2. Si VLSI fab and ESH protocols have been developed to enable advanced process flows.

Keywords

CMOS logic circuits; III-V semiconductors; VLSI; elemental semiconductors; low-power electronics; nanotechnology; silicon; ESH protocols; III-V materials; Si; Si VLSI fab; advanced CMOS logic; low power; nanotechnology node; size 10 nm; transport properties; Doping; Junctions; Logic gates; Plasmas; Silicon; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems, and Applications (VLSI-TSA), 2012 International Symposium on

Conference_Location

Hsinchu

ISSN

1930-8868

Print_ISBN

978-1-4577-2083-3

Type

conf

DOI

10.1109/VLSI-TSA.2012.6210160

Filename

6210160