Title :
Improvements in low temperature (<625°C) FDSOI devices down to 30nm gate length
Author :
Xu, C. ; Batude, P. ; Vinet, M. ; Mouis, M. ; Casse, M. ; Sklénard, B. ; Colombeau, B. ; Rafhay, Q. ; Tabone, C. ; Berthoz, J. ; Previtali, B. ; Mazurier, J. ; Brunet, L. ; Brevard, L. ; Khaja, F.A. ; Hartmann, J. -M ; Allain, F. ; Toffoli, A. ; Kies, R.
Author_Institution :
LETI, CEA, Grenoble, France
Abstract :
For the first time, low temperature (LT) anneal at 625°C has been demonstrated for dopants activation enabling similar ION/IOFF trade-off as standard spike anneal (>;1000°C), down to 30nm gate length (LG) for both n&p FETs. Similar short channel effect control has been achieved in LT n&p FETs as its high temperature (HT) counterparts. Influence of dopant implant tilt on LT device performance is analyzed and guidelines for device performance optimization are proposed. This demonstration paves the way to 3D sequential integration with equal performance for stacked transistors and for bottom transistors.
Keywords :
annealing; field effect transistors; ion implantation; optimisation; silicon-on-insulator; 3D sequential integration; LT n&p FET; Si; bottom transistors; dopant implant tilt; dopants activation; low temperature FDSOI devices; low temperature anneal; optimization; short channel effect; size 30 nm; stacked transistors; temperature 625 degC; Annealing; FETs; Implants; Logic gates; Performance evaluation; Silicon; Standards;
Conference_Titel :
VLSI Technology, Systems, and Applications (VLSI-TSA), 2012 International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
978-1-4577-2083-3
DOI :
10.1109/VLSI-TSA.2012.6210171
