Title :
Key enabling technologies of 300mm 3DIC process integration
Author :
Tzeng, Pei-Jer ; Hsin, Yu-Chen ; Chen, Jui-Chin ; Chen, Shang-Chun ; Wu, Chien-Ying ; Tsai, Wen-Li ; Wang, Chung-Chih ; Ho, Chi-Hon ; Chen, Chien-Chou ; Hsu, Yi-Feng ; Shen, Shang-Hung ; Liao, Sue-Chen ; Chien, Chun-Hsien ; Chang, Hsiang-Hung ; Lin, Cha-H
Author_Institution :
Electron. & Optoelectron. Res. Labs., Ind. Technol. Res. Inst., Hsinchu, Taiwan
Abstract :
Process issues and challenges of three-dimensional integrated circuit (3DIC) using through-silicon-via (TSV) are extensively investigated. Key enabling process technologies in the TSV formation and thin wafer handling are discussed with a viewpoint of TSV process integration. Test element groups (TEG) are designed to characterize the process performance and optimizations of some key process modules are also provided as process guidelines.
Keywords :
circuit optimisation; integrated circuit design; integrated circuit testing; three-dimensional integrated circuits; 3DIC process integration; TEG; TSV formation; TSV process integration; process guideline; process module; process optimization; process performance; size 300 mm; test element groups; thin wafer handling; three-dimensional integrated circuit; through-silicon-via; Bonding; Etching; Joints; Silicon; Substrates; Temperature; Through-silicon vias;
Conference_Titel :
VLSI Technology, Systems, and Applications (VLSI-TSA), 2012 International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
978-1-4577-2083-3
DOI :
10.1109/VLSI-TSA.2012.6210173
