The effect of static and dynamic parasitic charge in the termination area of high voltage devices and possible solutions

Author

Trajkovic, T. ; Udrea, F. ; Waind, P.R. ; Amaratunga, G.A.J.

Author_Institution

Dept. of Eng., Cambridge Univ., UK

fYear

2000

fDate

2000

Firstpage

263

Lastpage

266

Abstract

Parasitic charge in the passivation layer or at the interface may severely degrade the breakdown capability of high voltage devices. This is attributed to the change of the electric field contours in the presence of the interface charge from an optimal distribution to an unbalanced distribution. A solution to minimise this effect is proposed in this paper. The proposed breakdown termination technique can be used in a wide range of devices such as power MOSFETs, IGBTs or MOS-controlled thyristors and it is especially effective at voltages above 1.2 kV when the n-drift concentration is reduced

Keywords

MOS-controlled thyristors; electric charge; insulated gate bipolar transistors; interface phenomena; passivation; power MOSFET; power semiconductor devices; protection; semiconductor device breakdown; 1.2 kV; HV devices; IGBTs; MOS-controlled thyristors; breakdown capability; breakdown termination technique; dynamic parasitic charge; electric field contours; high voltage devices; interface charge; n-drift concentration reducetion; optimal distribution; parasitic charge protection termination; passivation layer charge; power MOSFETs; static parasitic charge; termination area; unbalanced distribution; Breakdown voltage; Degradation; Electric breakdown; Insulated gate bipolar transistors; Leakage current; MOSFETs; Passivation; Robustness; Thyristors; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Semiconductor Devices and ICs, 2000. Proceedings. The 12th International Symposium on

Conference_Location

Toulouse

ISSN

1063-6854

Print_ISBN

0-7803-6269-1

Type

conf

DOI

10.1109/ISPSD.2000.856821

Filename

856821