A CMOS Differential Difference Amplifier with Reduced Nonlinearity Error of Interpolation for Interpolating ADCs

Author

Zhang, Xin ; Yu, Dunshan ; Sheng, Shimin

Author_Institution

Inst. of Microelectron., Peking Univ., Beijing

fYear

2006

fDate

4-7 Dec. 2006

Firstpage

9

Lastpage

12

Abstract

In this paper, the nonlinearity error induced by interpolation amplifier in interpolating analog-to-digital converters (ADCs) is analyzed, and a new differential difference amplifier (DDA) with well restrained nonlinearity error is presented. Its highly steady common-mode output voltage makes it especially suitable for differential interpolating ADCs. The amplifier is designed in a 0.35mum standard CMOS process with a single 3.3V supply. Simulated results show that this amplifier achieves a steady common-mode output in a wide common-mode input range from 0.85V to 2.45V without demanding complex circuitry. The amplifier settles in 4.8ns to an accuracy of 0.01% and dissipates a total power of 398.38muW

Keywords

CMOS analogue integrated circuits; analogue-digital conversion; differential amplifiers; interpolation; 0.35 micron; 0.85 to 2.45 V; 3.3 V; 398.38 muW; 4.8 ns; CMOS differential difference amplifier; CMOS process; common-mode input range; common-mode output voltage; interpolating ADC; interpolating analog-to-digital converters; interpolation amplifier; nonlinearity error; Analog-digital conversion; CMOS process; Circuit simulation; Differential amplifiers; Interpolation; Microelectronics; Noise reduction; Power amplifiers; Virtual reality; Voltage; amplifier; interpolating ADC; nonlinearity error;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on

Conference_Location

Singapore

Print_ISBN

1-4244-0387-1

Type

conf

DOI

10.1109/APCCAS.2006.342250

Filename

4145319