A Fast-Lock-In ADPLL with High-Resolution and Low-Power DCO for SoC Applications

Author

Sheng, XDuo ; Chung, Ching-Che ; Lee, Chen-Yi

Author_Institution

Dept. of Electron. Eng., Nat/ Chiao Tung Univ., Hsinchu

fYear

2006

fDate

4-7 Dec. 2006

Firstpage

105

Lastpage

108

Abstract

This paper proposed a fast-lock-in all-digital phase-locked loop (ADPLL), which is designed with the cell library and described by hardware description language (HDL). The proposed ADPLL uses a novel 2-level flash time-to-digital converter (TDC) to lock in within 2 reference clock cycles. The novel digitally controlled oscillator (DCO) achieves high-resolution with 0.93ps resolution and can extend the controllable range easily. In addition to high-resolution, the power consumption of the proposed DCO can be lowered as 110muW(@200MHz). The proposed ADPLL can be easily ported to different process as a soft intellectual property (IP), making it very suitable for system-on-chip (SoC) applications as well as system-level power management

Keywords

digital phase locked loops; hardware description languages; oscillators; system-on-chip; 110 muW; 200 MHz; DCO; HDL; SoC applications; all-digital phase-locked loop; cell library; digitally controlled oscillator; flash time-to-digital converter; hardware description language; soft intellectual properties; system-level power management; Clocks; Digital control; Energy consumption; Energy management; Hardware design languages; Intellectual property; Oscillators; Phase locked loops; Software libraries; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on

Conference_Location

Singapore

Print_ISBN

1-4244-0387-1

Type

conf

DOI

10.1109/APCCAS.2006.342325

Filename

4145343