An Efficient Clocking Scheme for On-Chip Communications

In globally asynchronous locally synchronous (GALS) architectures, system on chip (SoC) deals with the risk of synchronization failure for the locally generated clocks. Also, this is an issue for networks on chips (NoCs). This paper proposes an efficient synchronizer for on-chip communication. The proposed module can be used in NoC switches satisfying the requirements for designing GALS SoCs. Proposed architecture is based on mesochronous clocking scheme and can endure frequency drift between two clock domains. Efficiency of the proposed architecture is evaluated by implementing in 0.18mum CMOS technology. In comparison with a similar architecture, based on delay locked loop (DLL), the new architecture saves around 74% of power consumption. Such power reduction is achieved while the number of transistors is decreased about 29% rather than the DLL-based architecture