Title :
New performance driven routing techniques with explicit area/delay tradeoff and simultaneous wire sizing
Author :
Lillis, John ; Cheng, Chung-Kuan ; Lin, Ting-Ting Y. ; Ho, Ching-Yen
Author_Institution :
Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
Abstract :
We present new algorithms for construction of performance driven Rectilinear Steiner Trees under the Elmore delay model. Our algorithms represent a departure from previous approaches in that we derive an explicit area/delay trade-off curve. We achieve this goal by limiting the solution space to the set of topologies induced by a permutation on the sinks of the net. This constraint allows efficient identification of optimal solutions while still providing a rich solution space. We also incorporate simultaneous wire sizing. Our technique consistently produces topologies equalling the performance of previous approaches with substantially less area overhead
Keywords :
circuit layout CAD; integrated circuit interconnections; network routing; Elmore delay model; Rectilinear Steiner Trees; area overhead; area/delay tradeoff; performance driven; routing techniques; simultaneous wire sizing; solution space; Delay effects; Delay lines; Large scale integration; Logic; Permission; Routing; Solid modeling; Topology; Very large scale integration; Wire;
Conference_Titel :
Design Automation Conference Proceedings 1996, 33rd
Conference_Location :
Las Vegas, NV
Print_ISBN :
0-7803-3294-6
DOI :
10.1109/DAC.1996.545608