DocumentCode :
2240210
Title :
Network partitioning into tree hierarchies
Author :
Kuo, Ming-Ter ; Liu, Lung-Tien ; Cheng, Chung-Kuan
Author_Institution :
Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
fYear :
1996
fDate :
3-7 Jun, 1996
Firstpage :
477
Lastpage :
482
Abstract :
This paper addresses the problem of partitioning a circuit into a tree hierarchy with an objective of minimizing a global interconnection cost. An efficient and effective algorithm is necessary when the circuit is huge and the tree has many levels of hierarchy. We propose a heuristic algorithm for improving a partition with respect to a given tree structure. The algorithm utilizes the tree hierarchy as an efficient mechanism for iterative improvement. We also extend the tree hierarchy to apply a multi-phase partitioning approach. Experimental results show that the algorithm significantly improves the initial partitions produced by multiway partitioning and by recursive partitioning
Keywords :
circuit CAD; integrated circuit design; logic CAD; logic partitioning; global interconnection cost; heuristic algorithm; iterative improvement; multi-phase partitioning approach; multiway partitioning; network partitioning; recursive partitioning; tree hierarchies; tree hierarchy; Computer science; Costs; Heuristic algorithms; Integrated circuit interconnections; Iterative algorithms; Iterative methods; Partitioning algorithms; Permission; Pins; Tree data structures;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference Proceedings 1996, 33rd
Conference_Location :
Las Vegas, NV
ISSN :
0738-100X
Print_ISBN :
0-7803-3294-6
Type :
conf
DOI :
10.1109/DAC.1996.545623
Filename :
545623
Link To Document :
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