A Fast 1.9 GHz Fractional-N/Integer Frequency Synthesizer with a Self-tuning Algorithm

Author

Huang, Shuilong ; Wang, ZhiHua ; Ma, Huainan

Author_Institution

Dept. of Electron. Eng., Tsinghua Univ., Beijing

fYear

2006

fDate

4-7 Dec. 2006

Firstpage

203

Lastpage

206

Abstract

A self-tuning, adaptive 1.9GHz fractional-N/integer frequency synthesizer is proposed in the paper. A combined tuning technique of digital tuning and analog tuning is used to decrease the gain of VCO. The adaptive loop is introduced for automatic adjustment of the loop bandwidth. Two operation modes (fractional-N/integer) are achieved by switching on/off the output signal of SigmaDelta modulator. Just a programmable counter is needed for the swallow pulse divider. Based on 0.18 mum 1.8V CMOS technology. Simulation shows that the frequency synthesizer has a 100 KHz loop bandwidth, a <15mus settling time, and the phase noise is lower than -123dBc@ 600 KHz

Keywords

CMOS integrated circuits; circuit tuning; frequency synthesizers; programmable circuits; sigma-delta modulation; voltage-controlled oscillators; 0.18 micron; 1.8 V; 1.9 GHz; 100 kHz; 600 kHz; CMOS technology; SigmaDelta modulator; adaptive loop; analog tuning; digital tuning; fractional-N/integer frequency synthesizer; loop bandwidth; programmable counter; self-tuning algorithm; swallow pulse divider; voltage controlled oscillator; Bandwidth; Charge pumps; Counting circuits; Filters; Frequency synthesizers; Phase frequency detector; Phase locked loops; Phase noise; Tuning; Voltage-controlled oscillators; Adaptive; Divider; Frequency synthesizer; PFD; Self-tuning;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on

Conference_Location

Singapore

Print_ISBN

1-4244-0387-1

Type

conf

DOI

10.1109/APCCAS.2006.342367

Filename

4145366