An ASIC Implementation of Lifting-Based 2-D Discrete Wavelet Transform

Author

Leibo Liu ; Hongying Meng ; Milin Zhang

Author_Institution

Inst. of Microelectron., Tsinghua Univ., Beijing

fYear

2006

fDate

4-7 Dec. 2006

Firstpage

271

Lastpage

274

Abstract

An ASIC implementation of spatial combinative lifting algorithm (SCLA) based 2D forward and inverse discrete wavelet transform (DWT) with both 5/3 and 9/7 filters and 5-level Mallat decomposition is proposed in this paper. This processor is fabricated in a 1.5mm times 1.5 mm die, using UMC 0.18mum CMOS technology, containing 28K gates plus 47Kbits on-chip SRAM. Test shows this chip can process at 23.29 frames/s with image resolution up to 1920times1080 pixels (YUV422 full color) under 100MHz, and consuming 50mW under a 1.8V power supply

Keywords

CMOS integrated circuits; SRAM chips; application specific integrated circuits; coprocessors; discrete wavelet transforms; filters; integrated circuit manufacture; 0.18 micron; 1.5 mm; 1.8 V; 100 MHz; 2D discrete wavelet transform; 47 kbit; 5-level Mallat decomposition; 5/3 filter; 50 mW; 9/7 filter; ASIC; CMOS technology; YUV422 full color; on-chip SRAM; processor; spatial combinative lifting algorithm; Application specific integrated circuits; CMOS process; CMOS technology; Color; Discrete wavelet transforms; Filters; Image resolution; Pixel; Random access memory; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on

Conference_Location

Singapore

Print_ISBN

1-4244-0387-1

Type

conf

DOI

10.1109/APCCAS.2006.342403

Filename

4145383