Issues for multilevel metallization in high density circuits

Summary form only given. As lateral dimensions shrink in high density circuits, metal and dielectric film thicknesses are not shrinking at the same pace. This leads to several technological challenges in multilevel interconnects. Also, rising numbers of metal layers add to the process complexity and pose specific demands on the process technology. Some issues related to the challenges mentioned above are discussed in this paper. One important issue for state-of-the-art technology is that the aspect ratios for contacts and intermetal gaps are increasing from one technology generation to the next. Various methods are discussed that aim at achieving sufficient barrier/liner coverage in these high aspect ratio contacts/vias. Options for contact and via fill processes are also discussed in this context.