Design and analysis of inductors for 60 GHz applications in a digital CMOS technology

Author

Scheir, Karen ; Wambacq, Piet ; Rolain, Yves ; Vandersteen, Gerd

Author_Institution

Dept. ELEC, Vrije Univ. Brussel, Brussels, Belgium

fYear

2007

fDate

8-8 June 2007

Firstpage

1

Lastpage

4

Abstract

RFIC designers of on-chip transceivers for 60 GHz applications face the trade-off between lumped and distributed design techniques, due to the on-chip wavelength of approximately 3 mm. This paper demonstrates that the lumped approach is favorable for realizing 60 GHz inductive components in digital CMOS technologies. Advantages in area consumption, Q-factor and the range of achievable component values are shown using simulations and measurements. Simulations of lumped inductors using the electromagnetic field solver HFSS are compared with measurements and different topologies for the lumped inductor are investigated and compared. The measurement results reveal that a planar unshielded topology yields the best inductor quality for 60 GHz circuits in a digital CMOS technology.

Keywords

CMOS digital integrated circuits; Q-factor; field effect MMIC; inductors; integrated circuit design; integrated circuit modelling; transceivers; HFSS; Q-factor; RFIC design; digital CMOS technology; distributed design technique; electromagnetic field solver; frequency 60 GHz; inductor design; lumped design technique; lumped inductor simulation; on-chip transceiver; planar unshielded topology; the on-chip wavelength; Area measurement; CMOS technology; Circuit simulation; Circuit topology; Electromagnetic measurements; Inductors; Q factor; Radiofrequency integrated circuits; Transceivers; Wavelength measurement; 60 GHz digital CMOS; mm-wave; monolithic inductors;

fLanguage

English

Publisher

ieee

Conference_Titel

ARFTG Conference, 2007 69th

Conference_Location

Honolulu, HI

Print_ISBN

978-0-7803-9762-0

Electronic_ISBN

978-0-7803-9763-7

Type

conf

DOI

10.1109/ARFTG.2007.5456340

Filename

5456340