Designing a reconfigurable architecture for ultra-low power wireless sensors

In wireless sensor network nodes all tasks are controlled and scheduled by the CPU of the node. It is activated repeatedly from its low-power sleep mode for e.g., measurements and communications tasks. The periodic wake-ups cause a high overhead in power consumption. This problem can be solved by supplementing the CPU with additional modules which autonomously execute selected tasks to enable the CPU to stay in its inactive low-power mode. It is only activated if more complex processing is required, e.g. for generating a network packet to transmit a changed sensor value. We introduce logic modules with a reconfigurable architecture which allow to flexibly adopt the functionality but still perform relatively complex tasks. This work presents the methodology for the design of these reconfigurable logic modules.