DocumentCode :
2241151
Title :
Sampling Dead Block Prediction for Last-Level Caches
Author :
Khan, Samira ; Tian, Yingying ; Jiménez, Daniel A.
Author_Institution :
Dept. of Comput. Sci., Univ. of Texas at San Antonio, San Antonio, TX, USA
fYear :
2010
fDate :
4-8 Dec. 2010
Firstpage :
175
Lastpage :
186
Abstract :
Last-level caches (LLCs) are large structures with significant power requirements. They can be quite inefficient. On average, a cache block in a 2MB LRU-managed LLC is dead 86% of the time, i.e., it will not be referenced again before it is evicted. This paper introduces sampling dead block prediction, a technique that samples program counters (PCs) to determine when a cache block is likely to be dead. Rather than learning from accesses and evictions from every set in the cache, a sampling predictor keeps track of a small number of sets using partial tags. Sampling allows the predictor to use far less state than previous predictors to make predictions with superior accuracy. Dead block prediction can be used to drive a dead block replacement and bypass optimization. A sampling predictor can reduce the number of LLC misses over LRU by 11.7% for memory-intensive single-thread benchmarks and 23% for multi-core workloads. The reduction in misses yields a geometric mean speedup of 5.9% for single-thread benchmarks and a geometric mean normalized weighted speedup of 12.5% for multi-core workloads. Due to the reduced state and number of accesses, the sampling predictor consumes only 3.1% of the of the dynamic power and 1.2% of the leakage power of a baseline 2MB LLC, comparing favorably with more costly techniques. The sampling predictor can even be used to significantly improve a cache with a default random replacement policy.
Keywords :
cache storage; program processors; LRU-managed LLC; bypass optimization; cache block; dead block replacement; last-level caches; leakage power; memory-intensive single-thread benchmarks; multicore workloads; partial tags; power requirements; program counters; sampling dead block prediction; sampling predictor; cache; dead block prediction; microarchitecture;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microarchitecture (MICRO), 2010 43rd Annual IEEE/ACM International Symposium on
Conference_Location :
Atlanta, GA
ISSN :
1072-4451
Print_ISBN :
978-1-4244-9071-4
Type :
conf
DOI :
10.1109/MICRO.2010.24
Filename :
5695535
Link To Document :
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